1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a structure of a MOS transistor having a high breakdown voltage.
2. Description of the Related Art
An example of the structure of a cross section of a conventional N-channel MOS transistor having a high breakdown voltage will be described with reference to FIG. 5.
P-type well 50 is formed on the surface of P-type semiconductor substrate 1. N-type source region 51 and N-type drain region 52, each having a concentration which is higher than that of well 50, are spaced apart from each other in the respective portions near the surface of well 50. N-type impurity diffusion layer 53, whose concentration is higher than that of well 50 and lower than that of drain region 52, is formed in a portion near the surface of well 50 in contact with the wall of drain region 52, which is near source region 51, and to substantially the same depth as that of drain region 52. Gate electrode 55 is formed directly on a channel region between diffusion layer 53 and source region 51 in well 50 through insulation layer 54. In a P-channel MOS transistor, as illustrated in FIG. 7, it is necessary only to set well 46, drain region 47, source region 56 and impurity diffusion layer 57 in a conductive state opposite to that of the N-channel MOS transistor.
A vertical MOS transistor is used as a transistor requiring a breakdown voltage which is higher than that of the above-mentioned MOS transistor. An example of the structure of a cross section of the vertical MOS transistor is shown in FIG. 6. In FIG. 6, N-type buried layer 58 of high impurity concentration is formed in the surface of P-type semiconductor substrate 1 of low impurity concentration. N-type epitaxial layer 59 whose impurity concentration is lower than that of buried layer 58 is formed on the surfaces of substrate 1 and buried layer 58. Deep N-layer 60 having a concentration which is higher than that of epitaxial layer 59 and lower than that of buried layer 58, is formed from the end portion of buried layer 58 to the surface of epitaxial layer 59. P-type back gate layer 61 serving as a channel region is formed in a portion near the surface of epitaxial layer 59 surrounded by deep N-layers 60 and along deep N-layer 60. N-type source region 62 and P-type diffusion layer 63 each having a concentration which is higher than that of back gate layer 61, are formed in P-type back gate layer 61. Drain region 64, whose concentration is higher than that of deep N-layer 60, is formed in the surface portion of deep N-layer 60. Gate electrode 66 is formed directly on back gate layer 61 so as to interpose insulation layer 65 therebetween. Isolation layers 67 for isolating elements are formed in the surroundings of deep N-layer 60 from the surface of epitaxial layer 59 to the surface of semiconductor substrate 1.
In the conventional N-channel MOS transistor shown in FIG. 5, a depletion layer, which is formed at a drain PN junction when a reverse bias (drain voltage: +[V], gate voltage: 0[V], source voltage: 0[V]) is applied between the drain and source regions, has a shape shown by broken lines. The expansion of the depletion layer towards the channel region is more suppressed in a region between drain region 52 and well 50 where diffusion layer 53 of low concentration is formed than in a region where drain region directly contacts well 50. However, since the impurity concentration of diffusion layer 53 is higher than that of well 50, the depletion layer expands to the channel region and a high voltage is easily applied to insulation layer 54 directly under gate electrode 55. For this reason, the insulation breakdown voltage of insulation layer 54 is equal to the breakdown voltage of the MOS transistor and it is thus difficult to use the MOS transistor with a voltage which is higher than the breakdown voltage of insulation layer 54. If insulation layer 54 is thickened, its breakdown voltage can be increased, but a parasitic capacity becomes large and an operation speed becomes high. Taking this problem into consideration, a breakdown voltage of at most 40 V can be obtained in this MOS transistor.
If a reverse bias is applied to the vertical MOS transistor shown in FIG. 6 whose breakdown voltage is much higher than that of the above-mentioned MOS transistor, the depletion layer at the drain P-N junction does not expand so widely toward the channel region and a high breakdown voltage can thus be obtained since the impurity concentration of epitaxial layer 59 in the drain region is lower than that of back gate layer 61. However, this vertical MOS transistor requires the formation of Deep N-layer 60 serving as a drain region, thereby increasing an element in area. Furthermore, since epitaxial layer 59 is used in the drain region, it needs to be isolated from other elements. After isolation layer 67 is formed, an element must be formed therein. Since isolation layer 67 needs to deeply expand from epitaxial layer 59 to semiconductor substrate 1, the width of isolation layer 67 on the surface of epitaxial layer 59 is considerably large. When the thickness of epitaxial layer 59 is set to about 6 .mu.m which is substantially the same as that of a well layer of the present invention mentioned later, the width of isolation layer 67 is about 12 .mu.m which is twice as large as that of epitaxial layer 59. The width and depth of the isolation layer are very difficult to control and cannot be made constant. For this reason, the isolation layer is usually formed so as to have a space in an element-forming region and thus the element area is further enlarged, which prevents an improvement in the packed density.